all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 8-bit fast microcontrollers family ver 2.08 overview document contains brief description of df6811 core functionality. the df6811 is a advanced 8-bit mcu ip core with highly so- phisticated, on chip peripheral capabilities. df6811 soft core is binary-compatible with the industry standard 68hc11 8-bit microcontrol- ler and can achieve a performance 45-100 million instructions per second. df6811 has fast architecture that is 3.8 times faster compared to original implementation. core in standard configuration has integrated on chip major peripheral function. there are two serial interfaces: an asynchro- nous serial communications interface (sci) and a separate synchronous serial peripheral interface (spi). the main 16-bit, free-running timer system has implemented three input capture lines, five output-compare lines, and a real-time in- terrupt function. an 8-bit pulse accumulator subsystem can count external events or measure external periods. self-monitoring circuitry is included on-chip to protect against system errors. a computer operating properly (cop) watchdog system protects against software failures. an illegal opcode detection circuit provides a non- maskable interrupt if illegal opcode is de- tected. two software-controlled power-saving modes, wait and stop, are available to conserve additional power. these modes make the df6811 ip core especially attractive for automotive and battery-driven applications. the df6811 have built in the development support features designed into df6811. the lir signal is intended as a debugging aid. this signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) in- structions from the display of a logic analyzer. df6811 is fully customizable , which means it is delivered in the exact configuration to meet users requirements. there is no need to pay extra for not used features and wasted silicon. it includes fully automated testbench with complete set of tests allowing easy package validation at each stage of soc de- sign flow. cpu features fast architecture, 3,8 times faster than the original implementation software compatible with industry standard 68hc11 10 times faster multiplication 16 times faster division 64 bytes of remapped system function registers space (sfrs) up to 16m bytes of data memory de-multiplexed address/data bus to allow easy connection to memory two power saving modes: stop, wai
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. user programmable external data memory write and read pulses between 1 to 8 clock periods fully synthesizable, static synchronous design with no internal tri-states no internal reset generator or gated clock scan test ready technology independent hdl source code core can be fully customized design features ? o ne global system clock ? s ynchronous reset the df6811 has 3 reset vectors sources, which easy identify a cause of system reset. ? a ll asynchronous input signals are synchronized before internal use ? d ata m emory : the df6811 can address up to 16m bytes of data memory via the function in- terconnect signals. the 64 bytes of data memory in every 64k page is reserved for the function registers. extra dpp (data page pointer) register is used for segments swapping. data memory can be imple- mented as synchronous or asynchronous. peripherals the peripherals listed below are not imple- mented in standard configuration of df6811. they can be integrated in core as a option. four 8-bit i/o ports interrupt controller 20 interrupt sources 17 priority levels dedicated interrupt vector for each interrupt source main16-bit timer/counter system 16 bit free running counter four stage programmable prescaller timer clocked by internal source real time interrupt 16-bit compare/capture unit three independent input-capture functions five output-compare channels events capturing pulses generation digital signals generation gated timers sophisticated comparator pulse width modulation pulse width measuring 8-bit pulse accumulator two major modes of operation simple event counter gated time accumulation clocked by internal source or external pin full-duplex uart - sci standard nonreturn to zero format (nrz) 8 or 9 bit data transfer integrated baud rate generator enhanced receiver data sampling technique noise, overrun and framing error detection idle and break characters generation wake-up block to recognize uart wake-up from idle condition three sci related interrupts spi ? master and slave serial peripheral interface supports speeds up ? of system clock mode fault error write collision error software selectable polarity and phase of se- rial clock sck system errors detection allows operation from a wide range of system clock frequencies (build-in 5-bit timer) interrupt generation
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. deliverables ? source code: ? vhdl source code or/and ? verilog source code or/and ? encrypted, or plain text edif netlist ? vhdl & verilog test bench environ- ment ? active-hdl automatic simulation macros ? modelsim automatic simulation macros ? tests with reference responses ? technical documentation ? installation notes ? hdl core specification ? datasheet ? synthesis scripts ? example application ? technical support ? ip core implementation support ? 3 months maintenance delivery the ip core updates, minor and major versions changes delivery the documentation updates phone & email support configuration the following parameters of the df6811 core can be easy adjusted to requirements of dedicated application and technology. con- figuration of the core can be prepared by ef- fortless changing appropriate constants in package file. there is no need to change any parts of the code. - 64 kb data memory size - 16 mb - used (0-7) data memory wait-states - unused - used power saving stop mode - unused - used watchdog timer - unused - used timer system - unused - used compare capture channels - unused - used pulse accumulator - unused - used ports a, b, c, d - unused - used sci ? uart interface - unused - used spi interface - unused - used support for idiv instruction - unused - used support for fdiv instruction - unused - used support for mul instruction - unused - used support for daa instruction - unused licensing comprehensible and clearly defined licensing methods without royalty fees make using of ip core easy and simply. single design license allows use ip core in single fpga bitstream and asic implementa- tion. unlimited designs , one year licenses allow use ip core in unlimited number of fpga bit- streams and asic implementations. in all cases number of ip core instantiations within a design, and number of manufactured chips are unlimited. there is no time restric- tion except one year license where time of use is limited to 12 months. single design license for vhdl, verilog source code called hdl source encrypted,or plain text edif called netlist one year license for encrypted netlist only unlimited designs license for hdl source netlist upgrade from hdl source to netlist single design to unlimited designs
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. pins description pin active type description clk - input global system clock rst low input global system reset datai[7:0] - input external memory bus input ufrdatai[7:0] - input ufrs data bus input por low input power on reset vector fetch copi low input cop timeout vector fetch cmf low input clock monitor fail vector fetch datai[7:0] - input external memory bus input ufrdatai[7:0] - input ufrs data bus input irq * input interrupt input xirq low input non-maskable interrupt input portai[7:0] - input port a input portbi[7:0] - input port b input portci[7:0] - input port c input portdi[7:0] - input port d input cap1,2,3 low input capture inputs pai * input pulse accumulator input rxd low input sci receiver data input si high input spi slave input mi high input spi master input scki * input spi clock input ss low input spi slave select datao[7:0] - output data memory & ufr bus output addr[23:0] - output data memory & fr address bus ramwe low output memory write enable ramoe low output memory output enable ufrwe low output ufrs write enable ufroe low output ufrs output enable lir low output load instruction register halt high output halt clock system (stop inst.) cme high output clock monitor enable copo low output watchdog timeout output cmp1,2,3,4,5 * output compare outputs cmp1z,2,3,4,5 high output disconnect output compare portxo[7:0] - output port a, b, c, d output ddrx[7:0] - output port a, b,c,d data direction control cmp1,2,3,4,5 * output compare outputs cmp1z,2,3,4,5 high output disconnect output compare txd low output sci transmitter data output so high output spi slave output mo high output spi master output scko * output spi clock output sckz high output disconnect spi clock output * kind of activity is configurable symbol ramwe ramoe ufrwe ufroe portao(7:0) portdo(7:0) portco(7:0) portbo(7:0) portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) datai(7:0) ufrdatai(7:0) irq xirq pai cap1 cap2 cap3 clk rst rxd datao(7:0) addr(23:0) txd si mi so mo scki scko sckz ss por copi cmf halt cme ddra(7:0) ddrd(7:0) ddrc(7:0) ddrb(7:0) cmp1z cmp2z cmp3z cmp4z cmp5z cmp1 cmp2 cmp3 cmp4 cmp5 li r copo block diagram control unit - performs the core synchroniza- tion and data flow control. this module man- ages execution of all instructions. the control unit also manages execution of stop instruc- tion and waking-up the processor from the stop mode. opcode decoder - performs an instruction opcode decoding and the control functions for all other blocks .
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. alu - arithmetic logic unit performs the arithmetic and logic operations during execu- tion of an instruction. it contains accumulator (a, b), condition code register (ccreg), index registers x, y and related logic such as arithmetic unit, logic unit, multiplier and di- vider. portao(7:0) portdo(7:0) portco(7:0) portbo(7:0) datai(7:0) clk rst datao(7:0) cap1 cap2 cap3 ram & sfr control i/o ports opcode decoder control unit interrupt controller timer with compare / capture unit sci unit spi unit irq por cmp1 cmp2 cmp3 cmp4 cmp5 cmp1z cmp2z cmp3z cmp4z cmp5z txd rxd mo so si scki mi scko sckz cme xirq ramoe ramwe addr(23:0) ss halt cm f copi portai(7:0) portdi(7:0) portci(7:0) portbi(7:0) li r ddra(7:0) ddrd(7:0) ddrc(7:0) ddrb(7:0) watchdog timer pulse accumulator pai copo alu ufroe ufrwe ram & sfr controller - data memory & sfr (special function register) interface controls access into the internal and external program and data memories and special reg- isters. it contains stack pointer (sp) register, init register (init), data page pointer (dpp), stretch register (st) and related logic. interrupt controller - df6811 extended ic has implemented 17-level interrupt priority control. the interrupt requests may come from external pins (irq and xirq) as well as from particular peripherals. the df6811 peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (i) in the ccr is cleared. maskable interrupts are prioritized according to default arrangement (look at the table below) estab- lished during reset. however any one source may be elevated to the highest maskable pri- ority position using hprio register. when interrupt condition occurs, an interrupt status flag is set to indicate the condition. and di- vider. timer, compare capture & cop watchdog - this timer system is based on a free-running 16-bit counter with a 4-stage programmable prescaler. a timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the coun- ter. three independent input-capture functions are used to automatically record the time when a selected transition is detected at a respective timer input pin. five output- compare functions are included for generating output signals or for timing software delays. since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in greater detail. a programmable periodic interrupt circuit called rti is tapped off of the main 16-bit timer counter. software can select one of four rates for the rti, which is most commonly used to pace the execution of software rou- tines. the cop watchdog function is loosely related to the main timer in that the clock input to the cop system (clk*2 17 ) is tapped off the free-running counter chain. the timer subsystem involves more registers and control bits than any other subsystem on the mcu. each of the three input-capture functions has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions has its own 16-bit compare register. all timer functions, including the timer overflow and rti, have their own interrupt controls and separate interrupt vec- tors. additional control bits permit software to control the edge(s) that trigger each input- capture function and the automatic actions that result from output-compare functions. although hardwired logic is included to auto- mate many timer activities, this timer architec- ture is essentially a software-oriented system. this structure is easily adaptable to a very wide range of applications although it is not as
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. efficient as dedicated hardware for some spe- cific timing applications. and divider. sci - the sci is a full-duplex uart type asynchronous system, using standard non return to zero (nrz) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. the df6811 resyn- chronizes the receiver bit clock on all one to zero transitions in the bit stream. therefore differences in baud rate between the sending device and the sci are not as likely to cause reception errors. three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. for the start and stop bits seven logic sam- ples are taken. even if noise causes one of these samples to be incorrect, the bit will still be received correctly. the receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. logic auto- matically wakes up the receiver in time to see the first character of the next message. this wakeup feature greatly reduces cpu over- head in multi-drop sci networks. the sci transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). in addition to the usual transmit data register empty (tdre) status flag, this sci also provides a transmit complete (tc) indication that can be used in applications with a modem. spi unit ? it?s a fully configurable mas- ter/slave serial peripheral interface, which allows user to configure polarity and phase of serial clock signal sck. it allows the micro- controller to communicate with serial periph- eral devices. it is also capable of interproces- sor communications in a multi-master system. a serial clock line (sck) synchronizes shifting and sampling of the information on the two independent serial data lines. spi data are simultaneously transmitted and received. spi system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. data rates as high as clk/4. clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. when the spi is configured as a master, software selects one of four different bit rates for the serial clock. spi automatically drives slave select outputs sso[7:0], and address spi slave device to exchange serially shifted data. error-detection logic is included to support interprocessor communications. a write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. a multiple-master mode-fault detector automatically disables spi output drivers if more than one spi devices simulta- neously attempts to become bus master. pulse accumulator ? this system is based on an 8-bit counter and can be configured to operate as a simple event counter or for gated time accumulation. unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). control bits allow the user to configure and control the pulse accumulator subsystem. two maskable interrupts are associated with the system, each having its own controls and interrupt vector. the pai pin associated with the pulse accumulator can be configured to act as a clock (event counting mode) or as a gate sig- nal to enable a free-running e divided by 64 clock to the 8-bit counter (gated time accumu- lation mode). the alternate functions of the pulse accumulator input (pai) pin present some interesting application possibilities. i/o ports - all ports are 8-bit general-purpose bi-directional i/o system. the porta, portb, portc, portd data registers have their corresponding data direction registers ddra, ddrb, ddrc, ddrd to control ports data flow. it assures that all df6811?s ports have full i/o selectable registers. writes to any ports pins cause data to be stored in the data registers. if any port pins are configured as output then data registers are driven out of those pins. reads from port pins configured as input causes that input pin is read. if port pins is configured as output, during read data register is read. writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. thus, if the pins later become outputs, the last data written to port will be driven out the port pins.
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. optional peripherals there are also available an optional pe- ripherals, not included in presented df6811 microcontroller core. the optional peripherals, can be implemented in microcontroller core upon customer request. pwm ? pulse width modulation timer 2 independent 8-bit pwm channels, concate- nated on one 16-bit pwm channel software-selectable duty from 0% to 100% and pulse period software-selectable polarity of output wave- form i2c bus controller - master 7-bit and 10-bit addressing modes normal, fast, high speeds multi-master systems supported clock arbitration and synchronization user defined timings on i2c lines wide range of system clock frequencies interrupt generation i2c bus controller - slave normal speed 100 kbs fast speed 400 kbs high speed 3400 kbs wide range of system clock frequencies user defined data setup time on i2c lines interrupt generation programmable watchdog timer fixed-point arithmetic coprocessor multiplication - 16bit * 16bit division - 32bit / 16bit division - 16bit / 16bit left and right shifting - 1 to 31 bits normalization floating-point arithmetic coprocessor ieee-754 standard single precision fadd, fsub - addition, subtraction fmul, fdiv- multiplication, division fsqrt- square root fucom - compare fchs - change sign fabs - absolute value floating-point math coprocessor - ieee- 754 standard single precision real, word and short integers fadd, fsub- addition, subtraction fmul, fdiv- multiplication, division fsqrt- square root fucom- compare fchs - change sign fabs - absolute value fsin, fcos- sine, cosine ftan, fatan ? tangent arcs tangent performance the following tables give a survey about the core area and performance in the asics and programmable logic devices after place & route (all cpu features and peripherals have been included): device speed grade f max orca 3t -7 8 mhz orca 4e -3 31 mhz ispxpga -5 30 mhz core performance in lattice? devices area utilized by the each unit of df6811 core in vendor specific technologies is summarized in table below. area component [lc / pfu] [ffs] cpu* 2300 / 340 311 main timer 83 / 14 50 com/cap 501 / 86 196 watchdog 72 / 13 30 pulse acc. 48 / 9 19 spi interface 135 / 24 60 uart - sci 326 / 60 131 i/o ports 157 / 28 96 total area 3300 / 574 893 *cpu ? consisted of alu, control unit and instruction decoder, bus controller with support for 16mb ram, external irq and xirq pin interrupt controller core components area utilization
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. improvement for user the most important is application speed improvement. the most commonly used arithmetic functions and theirs improve- ment are shown in table below. improvement was computed as {m68hc11 clock periods} divided by {df6811 clock peri- ods} required to execute an identical function. more details are available in core documenta- tion function improve- ment 8-bit addition ( immediate data ) 4 8-bit addition ( direct addressing ) 4 8-bit addition ( indirect addressing ) 4 8-bit subtraction ( immediate data ) 4 8-bit subtraction ( direct addressing ) 4 8-bit subtraction ( indirect addressing ) 4 16-bit addition ( immediate data ) 5,3 16-bit addition ( direct addressing ) 5 16-bit addition ( indirect addressing 4,8 16-bit subtraction ( immediate data ) 5,3 16-bit subtraction ( direct addressing ) 5 16-bit subtraction ( indirect addressing 4,8 multiplication 10 fractional division 14,9 integer division 16.4 df6811 family overview the main features of each df6811x family member have been summarized in table below. it gives a briefly member characterization helping user to select the most suitable ip core for its application. user can specify its own peripheral set (including listed below and the others) and requests the core modifications. design physical linear memory space paged data mem- ory space motorola memory expansion logic interrupt sources interrupt levels real time inter- rupt data pointers main timer sys- tem compare\capture sci (uart) i\o ports spi m/s interface watchdog timer pulse accumulator interface for additional sfrs df6811 64k 16m - 20 17 1* 1* 5/3* 1* 4 * * * DF6811CPU 64k 16m - 3 3 + 1* + + + + + + + df6811x family of high performance microcontroller cores + optional * configurable
all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. contacts for any modification or special request please contact to digital core design or local distributors. headquarters: wroclawska 94 41-902 bytom, poland e-mail: i i i n n n f f f o o o @ @ @ d d d c c c d d d . . . p p p l l l tel. : +48 32 282 82 66 fax : +48 32 282 74 37 field office: texas research park 14815 omicron dr. suite 100 san antonio, tx 78245,usa e-mail: i i i n n n f f f o o o u u u s s s @ @ @ d d d c c c d d d . . . p p p l l l tel. : +1 210 422 8268 fax : +1 210 679 7511 distributors: mtc - micro tech components gmbh am reitweg 15 89407 dillingen, germany e-mail : m m m t t t c c c i i i n n n f f f o o o @ @ @ m m m t t t c c c . . . d d d e e e tel. : +49 9071 7945-0 fax : +49 9071 7945-20 territory: germany, austria, switzerland
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